An 180 MHz 16 bit multiplier using asynchronous logic design techniques
An 180 MHz 16 bit multiplier using asynchronous logic design techniques
| dc.contributor.author | Burford, Richard G | |
| dc.contributor.author | Fan, Xingcha | |
| dc.contributor.author | Bergmann, Neil W | |
| dc.date.accessioned | 2011-12-07T23:41:10Z | |
| dc.date.available | 2011-12-07T23:41:10Z | |
| dc.date.issued | 1994 | |
| dc.description.abstract | A CMOS digital logic design technique is described which exploits the advantages of fast precharged logic and efficient latch design commonly used in synchronous systems while maintaining the features of localized control inherent in asynchronous design. A pipelined sixteen bit multiplier is presented and its performance compared with several previously reported asynchronous and synchronous designs. | en |
| dc.identifier.citation | Burford, R.G., Fan, X. and Bergmann, N.W. 1994. An 180 MHz 16 bit multiplier using asynchronous logic design techniques. 1994 Proceedings of the IEEE Custom Integrated Circuits Conference, 215-218. | en |
| dc.identifier.isbn | 780318862- | |
| dc.identifier.uri | http://hdl.handle.net/2328/25821 | |
| dc.language.iso | en | |
| dc.oaire.license.condition.license | In Copyright | |
| dc.publisher | Institute of Electrical and Electronics Engineers Computer Society (IEEE Publishing) | en |
| dc.subject | Logic design | en |
| dc.subject | Multiplying circuits | en |
| dc.subject | Pipeline arithmetic | en |
| dc.title | An 180 MHz 16 bit multiplier using asynchronous logic design techniques | en |
| dc.type | Article | en |