An 180 MHz 16 bit multiplier using asynchronous logic design techniques
An 180 MHz 16 bit multiplier using asynchronous logic design techniques
Date
1994
Authors
Burford, Richard G
Fan, Xingcha
Bergmann, Neil W
Journal Title
Journal ISSN
Volume Title
Publisher
Institute of Electrical and Electronics Engineers Computer Society (IEEE Publishing)
Abstract
A CMOS digital logic design technique is described which exploits the advantages of fast precharged logic and efficient latch design commonly used in synchronous systems while maintaining the features of localized control inherent in asynchronous design. A pipelined sixteen bit multiplier is presented and its performance compared with several previously reported asynchronous and synchronous designs.
Description
Keywords
Logic design,
Multiplying circuits,
Pipeline arithmetic
Citation
Burford, R.G., Fan, X. and Bergmann, N.W. 1994. An 180 MHz 16 bit multiplier using asynchronous logic design techniques. 1994 Proceedings of the IEEE Custom Integrated Circuits Conference, 215-218.