Architecture design of a fully asynchronous VLSI chip for DSP custom applications
Bergmann, Neil W
Institute of Electrical and Electronics Engineers Computer Society (IEEE Publishing)
A fully asynchronous, distributed VLSI architecture is introduced for dedicated real-time digital signal processing applications. The architecture is based on a data-driven computing model to allow maximum exploitation of the fine-grained concurrency. An asynchronous, self-time signaling protocol is used in the architecture to naturally match data-driven computing and circumvent the clock skew problem. After a brief description of the architecture, key issues of the architecture, such as the interconnection network, data identification, and operand matching are discussed. Finally, disadvantages of the architecture and future work are outlined.
Signal processing, Parallel architectures, Integrated circuits, Data analysis
Fan, X. and Bergmann, N. 1992. Architecture design of a fully asynchronous VLSI chip for DSP custom applications. 1992 Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), vol. 5, 2112 - 2115.